1. Field of the Invention
The present invention relates generally to a reduced-order circuit model and, more particularly, to a rapid and accurate reduced-order interconnect circuit model which can be used for signal analysis of a high-speed and very-large IC interconnect.
2. Description of Related Art
With rapid development of semiconductor techniques, the parasitic effect has no longer been ignored during design of high-speed and very-large IC interconnect. This technology was proposed in 2002 by M. Celik, L. T. and A. Odabasioglu “IC Interconnect Analysis,” Kluwer Academic Publisher.
Given the fact of more complex circuits, the corresponding order of mathematical models will be increased in order to accurately simulate the characteristics of interconnect circuits. Therefore, an efficient model reduction method has become a necessary know-how for interconnect modeling and simulation. The well-proven technologies, such as U.S. Pat. Nos. 6,789,237, 6,687,658, 6,460,165, 6,135,649, 6,041,170, 6,023,573, are proposed in 2000 by R. W. Freund, “Krylov-Subspace Methods for Reduced-Order Modeling in Circuit Simulation,” Journal of Computational and Applied Mathematics, Vol. 123, pp. 395-421; in 2002 by J. M. Wang, C. C. Chu, Q. Yu and E. S. Khu, “On Projection Based Algorithms for Model Order Reduction of Interconnects,” IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 49, No. 11, pp. 1563-1585.
In recent years, the common methods for circuit model reduction include:
Asymptotic Waveform Evaluation (AWE)(L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 4, pp. 352-366, 1990);
PVL (Pade via Lanczos)(P. Feldmann and R. W. Freund, “Efficient linear circuit analysis by Pad'e approximation via the Lanczos process,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14 pp. 639-649, 1995);
SyMPVL (Symmetric Matrix Pade via Lanczos)(P. Feldmann and R. W. Freund, “The SyMPVL algorithm and its applications to interconnect simulation,” Proc. 1997 Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 113-116, 1997);
Arnoldi Algorithm (e.g. U.S. Pat. No. 6,810,506); and
PRIMA (Passive Reduced-order Interconnect Macromodeling Algorithm)(A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: passive reduced-order interconnect macromodeling algorithm,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17 pp. 645-653, 1998).
All of the aforementioned model reduction techniques employ a Krylov Subspace Projection Method, which utilizes a projection operator to obtain the state variables of the reduced circuit system after projecting the state variable of the original circuit system. The projection operator is established by the Krylov Algorithm iteration process, of which the order of the reduced circuit is the number of iteration. For the model reduction algorithm of the applied projection method, another important job is to determine the order of the reduced circuit, since it is required to find out an appropriate order such that the reduced circuit can reflect accurately important dynamic behavior of the original circuit.